`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:17:29 03/28/2014 
// Design Name: 
// Module Name:    addrcalc 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////


module addrcalc_mc(hcounter, 
						vcounter,
						blank,
						addra,
						X1,
						Y1);
	
	input [10:0] 	X1,
						Y1;
		
	input  			blank;
	input signed [10:0] hcounter, 
								vcounter;
	output reg [12:0] addra;
	
		always @(hcounter,vcounter)
				begin
	
					if(hcounter>=X1 && hcounter<X1+45 && vcounter>=Y1 && vcounter<Y1+38)
						begin
							addra= (hcounter-X1)+(vcounter-Y1)*47;
						end
					else 
						begin
							addra=0;
						end
				end
	endmodule

